This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-181918, filed Jun. 16, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a cell transfer transistor of a DRAM, in particular, to a semiconductor memory provided with a vertical transistor and the method of manufacturing the same.
In the case of a cell transfer gate transistor of a DRAM having a stacked capacitor, in conformity with the miniaturization of the design rule, it is required to reduce the gate length in a manner equivalent to the minimum design rule. On this occasion, the threshold value of the cell transfer transistor is required to be kept substantially constant in view of the leak current to be generated when the transistor is in the state of OFF. On the other hand, in order to enable the threshold value of the cell transfer transistor to be kept constant, the concentration of the channel region impurity is required to be increased taking the short channel effects thereof into consideration. However, when the concentration of the channel region impurity is increased, it will lead to an increase of junction leak as well as to the deterioration of pose characteristics.
It is necessary, in order to suppress these phenomena, to employ a vertical transistor in place of the conventional planar transistor, thereby separating the gate length of the cell transfer transistor away from the minimum design rule. As one example of the vertical transistor, there is proposed xe2x80x9cA Surrounding Gate Transistor (SGT) Cell for 64/256 Mbit DRAMxe2x80x9d which is set forth on pages 23 through 26 of International Electron Device Meeting (IEDM) 1989 Technical Digest.
However, the memory cell constituted by the conventional vertical transistor has been manufactured in such a way that a silicon substrate is etched to form silicon columns, and transfer gates are formed around this silicon column. As a result, the manufacturing process thereof is relatively complicated, thus increasing the manufacturing cost thereof.
The present inventor has been accomplished in view of the aforementioned problems, and therefore, an object of this invention is to provide a semiconductor memory which is simply manufactured, and can be manufactured at low cost. Another object of this invention is to provide a method of manufacturing such a semiconductor memory.
Namely, according to a first aspect of this invention, there is provided a semiconductor memory which comprises:
an element isolation region constituted by an element isolating insulation film and selectively formed in a semiconductor substrate, thereby isolating an element region by the element isolation region;
a first diffusion region of a first conductivity type, which is formed on a surface of the element region;
a plurality of electrodes formed selectively on a surface of the semiconductor substrate;
a gate insulating film formed on the side wall and bottom face of the electrodes;
a monocrystalline silicon layer of a second conductivity type which is located between the electrodes, opposite sidewalls of the monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the monocrystalline silicon layer being contacted with the first diffusion region;
a second diffusion region of a first conductivity type, which is formed on a surface of the monocrystalline silicon layer; and
an insulating film formed on the electrodes, a top surface of the insulating film being flush with a top surface of the second diffusion region.
According to a second aspect of this invention, there is provided a semiconductor memory which comprises:
an element isolation region constituted by an element isolating insulation film and selectively formed in a semiconductor substrate, thereby isolating an element region by the element isolation region;
a first diffusion region of a first conductivity type, which is formed on a surface of the element region;
a plurality of electrodes formed selectively on a surface of the semiconductor substrate;
a gate insulating film formed on the side wall and bottom face of the electrodes;
a first monocrystalline silicon layer of a first conductivity type which is located between the electrodes, opposite sidewalls of the first monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the first monocrystalline silicon layer being contacted with the first diffusion region;
a second monocrystalline silicon layer of a second conductivity type which is located between the electrodes, opposite sidewalls of the second monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the second monocrystalline silicon layer being contacted with the first diffusion region and with the element isolation region;
a second diffusion region of a first conductivity type, which is formed on a surface of each of the first and second monocrystalline silicon layers; and
an insulating film formed on the electrodes, a top surface of the insulating film being flush with a top surface of the second diffusion region.
According to a third aspect of this invention, there is provided a semiconductor memory which comprises:
an element isolation region constituted by an element isolating insulation film and selectively formed in a semiconductor substrate, thereby isolating an element region by the element isolation region;
a first diffusion region of a first conductivity type, which is formed on a surface of the element region;
a third diffusion region of a second conductivity type, which is formed on a surface of the element region, the third diffusion region being contacted with the first diffusion region and with the element isolation region;
a plurality of electrodes formed selectively on a surface of the semiconductor substrate;
a gate insulating film formed on the side wall and bottom face of the electrodes;
a first monocrystalline silicon layer of a first conductivity type which is located between the electrodes, opposite sidewalls of the first monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the first monocrystalline silicon layer being contacted with the first diffusion region;
a second monocrystalline silicon layer of a second conductivity type which is located between the electrodes, opposite sidewalls of the second monocrystalline silicon layer being contacted with the gate insulating film, and a bottom face of the second monocrystalline silicon layer being contacted with the first diffusion region and with the third diffusion region;
a second diffusion region of a first conductivity type, which is formed on a surface of each of the first and second monocrystalline silicon layers; and
an insulating film formed on the electrodes, a top surface of the insulating film being flush with a top surface of the second diffusion region.
It is preferable, with semiconductor memories according to the aforementioned first and third aspects of this invention, to dispose the bottom face of the second diffusion region at a place which is lower than the bottom face of the insulating film.
In the semiconductor memory according to the first aspect of this invention, it may further comprise a storage node contact connected electrically with the second diffusion region; a capacitor connected electrically with the storage node contact; a bit line contact connected electrically with a portion of the second diffusion region other than the portion thereof which is electrically connected with the storage node contact; and a bit line connected electrically with the bit line contact.
On the other hand, in the semiconductor memory according to each of the second and third aspects of this invention, it may further comprise a storage node contact connected electrically with the second diffusion region formed on the surface of the second monocrystalline silicon layer; a capacitor connected electrically with the storage node contact; a bit line contact connected electrically with the second diffusion region formed on the surface of the first monocrystalline silicon layer; and a bit line connected electrically with the bit line contact.
According to a fourth aspect of this invention, there is provided a method of manufacturing a semiconductor memory which comprises:
selectively forming an element isolation region constituted by an element isolating insulation film in a semiconductor substrate, thereby isolating an element region by the element isolation region;
forming a sacrificial insulating film on a surface of the semiconductor substrate;
forming a first diffusion region of a first conductivity type on a surface of the element region;
forming a dummy layer on a surface of the sacrificial insulating film;
selectively etching the dummy layer to thereby form a first recessed portion exposing the surface of the element region and a second recessed portion exposing the surface of the element isolation region;
forming an interlayer insulating film in each of the first and second recessed portions;
removing the interlayer insulating film from the first recessed portion, thereby permitting the surface of the element region to be exposed;
forming a monocrystalline silicon layer of a second conductivity type in the first recessed portion by means of epitaxial growth;
removing the dummy layer to form a groove to thereby permit sidewalls of the monocrystalline silicon layer and a top surface of the element region to be exposed through the groove;
forming a gate insulating film on the exposed sidewalls of the monocrystalline silicon layer as well as on the exposed top surface of the element region;
forming a gate electrode in the groove;
removing an upper surface portion of the gate electrode;
forming an insulation film on a surface of the gate electrode where the top surface is removed; and
forming a second diffusion region of a first conductivity type on a surface of the monocrystalline silicon layer.
According to a fifth aspect of this invention, there is also provided a method of manufacturing a semiconductor memory which comprises the steps of:
selectively forming an element isolation region constituted by an element isolating insulation film in a semiconductor substrate, thereby isolating an element region by the element isolation region;
forming a sacrificial insulating film on a surface of the semiconductor substrate;
forming a first diffusion region of a first conductivity type on a surface of the element region;
forming a dummy layer on a surface of the sacrificial insulating film;
selectively etching the dummy layer to thereby form a first recessed portion exposing the surface of the element region, a second recessed portion exposing the surface of the element isolation region, and a third recessed portion exposing the surfaces of the element region and of the element isolation region;
forming an interlayer insulating film in each of the first, second and third recessed portions;
removing the interlayer insulating film from the first and third recessed portions, thereby permitting the surface of the element region to be exposed;
forming a first monocrystalline silicon layer in the first and third recessed portions by means of epitaxial growth;
removing the dummy layer to form a groove to thereby permit sidewalls of the first monocrystalline silicon layer and a top surface of the element region to be exposed through the groove;
forming a gate insulating film on the exposed sidewalls of the first monocrystalline silicon layer as well as on the exposed top surface of the element region;
forming a gate electrode in the groove;
performing an ion implantation of the first monocrystalline silicon layer, thereby forming a second monocrystalline silicon layer of a first conductivity type in the first recessed portion and also forming a third monocrystalline silicon layer of a second conductivity type in the third recessed portion;
removing an upper surface portion of the gate electrode;
forming an insulation film on a surface of the gate electrode where the top surface is removed; and
forming a second diffusion region of a first conductivity type on the surfaces of the second and third monocrystalline silicon layers.
According to a sixth aspect of this invention, there is also provided a method of manufacturing a semiconductor memory which comprises:
selectively forming an element isolation region constituted by an element isolating insulation film in a semiconductor substrate, thereby isolating an element region by the element isolation region;
forming a sacrificial insulating film on a surface of the semiconductor substrate;
forming a first diffusion region of a first conductivity type on a surface of the element region, thereby forming a second diffusion region of a second conductivity type at a surface region of the element region which neighbors on the element isolation region and on the first diffusion region;
forming a dummy layer on a surface of the sacrificial insulating film;
selectively etching the dummy layer to thereby form a first recessed portion exposing the surface of the first diffusion region, a second recessed portion exposing the surface of the element isolation region, and a third recessed portion exposing the surfaces of the first and second diffusion regions;
forming an interlayer insulating film in each of the first, second and third recessed portions;
removing the interlayer insulating film from the first and third recessed portions, thereby permitting the surface of the element region to be exposed;
forming a first monocrystalline silicon layer in the first and third recessed portions by means of epitaxial growth;
removing the dummy layer to form a groove to thereby permit sidewalls of the first monocrystalline silicon layer and a top surface of the element region to be exposed through the groove;
forming a gate insulating film on the exposed sidewalls of the first monocrystalline silicon layer as well as on the exposed top surface of the element region;
forming a gate electrode in the groove;
performing an ion implantation of the first monocrystalline silicon layer, thereby forming a second monocrystalline silicon layer of a first conductivity type in the first recessed portion and also forming a third monocrystalline silicon layer of a second conductivity type in the third recessed portion;
removing an upper surface portion of the gate electrode;
forming an insulation film on a surface of the gate electrode where the top surface is removed; and
forming a third diffusion region of a first conductivity type on the surfaces of the second and third monocrystalline silicon layers.
It is preferable, in the method of manufacturing a semiconductor memory according to the fourth, fifth and sixth aspects of this invention, that the film thickness of the sacrificial insulating film at the time of forming it should be made larger than the film thickness of the gate insulating film.
In the method of manufacturing a semiconductor memory according to the fourth, fifth and sixth aspects of this invention, the gate insulating film may be formed through the oxidation of the exposed sidewall of the monocrystalline silicon layer. Alternatively, the gate insulating film may be formed by way of the deposition of a high-melting point metal film.
The method of manufacturing a semiconductor memory according to the fourth aspect of this invention may further comprise, subsequent to the step of forming the monocrystalline silicon layer up to the level of the surface of the dummy layer by way of a selective epitaxial growth, a step of forming a polycrystalline silicon film on the aforementioned interlayer insulating film by way of non-selective epitaxial growth.
The methods of manufacturing a semiconductor memory according to the fifth and sixth aspects of this invention may further comprise, subsequent to the step of forming the first monocrystalline silicon layer up to the level of the surface of the dummy layer by way of a selective epitaxial growth, a step of forming a polycrystalline silicon film on the aforementioned interlayer insulating film by way of non-selective epitaxial growth.
As explained above, according to this invention, it is possible to provide a semiconductor memory and the method of manufacturing the same, which make it possible to simplify the manufacturing steps and to reduce the manufacturing cost.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.